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freescale semiconductor data sheet: technical data document number: mcf5329ds rev. 5, 11/2008 ? freescale semiconductor, inc., 2008. all rights reserved. mcf5329 mapbga?256 17mm x 17mm mapbga?196 15mm x 15mm features ? version 3 coldfire variable -length risc processor core ? system debug support ? jtag support for system level board testing ? on-chip memories ? 16-kbyte unified write-back cache ? 32-kbyte dual-ported sram on cpu internal bus, accessible by core and non-core bus masters (e.g., dma, fec, lcd controller, and usb host and otg) ? power management ? liquid crystal display controller (lcdc) ? embedded voice-over-ip (voip) system solution ? sdr/ddr sdram controller ? universal serial bus (usb) host controller ? universal serial bus (usb) on-the-go (otg) controller ? synchronous serial interface (ssi) ? fast ethernet controller (fec) ? cryptography hardware accelerators ? flexcan module ? three universal asynchronou s receiver transmitters (uarts) ?i 2 c module ? queued serial peripheral interface (qspi) ? pulse width modulation (pwm) module ? real time clock ? four 32-bit dma timers ? software watchdog timer ? four periodic interrupt timers (pits) ? phase locked loop (pll) ? interrupt controllers (x2) ? dma controller ? flexbus (external interface) ? chip configuration module (ccm) ? reset controller ? general purpose i/o interface mcf532 x coldfire ? microprocessor data sheet
mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 2 table of contents 1mcf532 x family comparison . . . . . . . . . . . . . . . . . . . . . . . . .3 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 hardware design considerations . . . . . . . . . . . . . . . . . . . . . . .5 3.1 pll power filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 usb power filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.3 supply voltage sequencing and separation cautions . .5 3.3.1 power up sequence . . . . . . . . . . . . . . . . . . . . . .5 3.3.2 power down sequence . . . . . . . . . . . . . . . . . . . .6 4 pin assignments and reset states . . . . . . . . . . . . . . . . . . . . .6 4.1 signal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4.2 pinout?256 mapbga . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3 pinout?196 mapbga . . . . . . . . . . . . . . . . . . . . . . . . .15 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .17 5.3 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5.4 dc electrical specifications . . . . . . . . . . . . . . . . . . . . .18 5.5 oscillator and pll electrical ch aracteristics . . . . . . . .19 5.6 external interface timing characteristics . . . . . . . . . . .20 5.6.1 flexbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.7 sdram bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.7.1 sdr sdram ac timing characteristics. . . . . .23 5.7.2 ddr sdram ac timing characteristics . . . . . 25 5.8 general purpose i/o timing . . . . . . . . . . . . . . . . . . . . 28 5.9 reset and configuration override timing . . . . . . . . . . 29 5.10 lcd controller timing specifications . . . . . . . . . . . . . 30 5.11 usb on-the-go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.12 ulpi timing specification . . . . . . . . . . . . . . . . . . . . . . 33 5.13 ssi timing specifications . . . . . . . . . . . . . . . . . . . . . . 33 5.14 i 2 c input/output timing specifications . . . . . . . . . . . . 35 5.15 fast ethernet ac timing specifications . . . . . . . . . . . 37 5.15.1 mii receive signal timing . . . . . . . . . . . . . . . . 37 5.15.2 mii transmit signal timing . . . . . . . . . . . . . . . . 37 5.15.3 mii async inputs signal timing . . . . . . . . . . . . 38 5.15.4 mii serial management channel timing . . . . . 38 5.16 32-bit timer module timing specifications . . . . . . . . . 39 5.17 qspi electrical specifications . . . . . . . . . . . . . . . . . . . 39 5.18 jtag and boundary scan timing . . . . . . . . . . . . . . . . 40 5.19 debug ac timing specifications . . . . . . . . . . . . . . . . . 42 6 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.1 package dimensions?256 mapbga . . . . . . . . . . . . . 45 7.2 package dimensions?196 mapbga . . . . . . . . . . . . . 46 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
mcf532x family comparison mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 3 figure 1. mcf5329 block diagram 1 mcf532 x family comparison the following table compares the various device derivatives available within the mcf532 x family. table 1. mcf532 x family configurations module mcf5327 mcf5328 mcf53281 mcf5329 coldfire version 3 core with emac (enhanced multiply-accumulate unit) ???? core (system) clock up to 240 mhz peripheral and external bus clock (core clock 3) up to 80 mhz performance (dhrystone/2.1 mips) up to 211 unified cache 16 kbytes static ram (sram) 32 kbytes flexbus d[31:0] a[23:0] r/w cs [5:0] ta ts xbs m2 m1 m0 m5 pwms, eport, jtag tap trst tclk tms tdi tdo cache (1024x32)x4 dma uarts flexcan i 2 c qspi dma timers watchdog, pits padi ? pin muxing extal xtal clkout 16 kbyte chip external selects (to/from padi) cantx canrx fec fec dma timer sdramc uart i 2 c sdramc qspi jtag_en rtc usb host m4 lcdc s4 s7 s1 reset ports sdramc ssi lcdc usb otg reset sram (4096x32)x2 32 kbyte pll s6 sdramc m6 usb host usb otg ulpi interface intc0 intc1 rcon lcdc ssi v3 coldfire cpu div emac bdm (to/from padi) rnga skha mdha cryptography modules interface rstout extal32k xtal32k (to/from sram backdoor) (to/from xbs backdoor) dreq n dack n (to/from padi) usb host usb otg b e/bwe [3:0] pwm xcvr xcvr (to/from padi)
mcf532x coldfire ? microprocessor data sheet, rev. 5 ordering information freescale semiconductor 4 2 ordering information lcd controller ? ? ? ? sdr/ddr sdram controller ? ? ? ? usb 2.0 host ? ? ? ? usb 2.0 on-the-go ? ? ? ? utmi+ low pin interface (ulpi) ? ? ? ? synchronous serial interface (ssi) ? ? ? ? fast ethernet controller (fec) ? ? ? ? cryptography hardware accelerators ? ? ? ? embedded voice-over-ip system solution ? ? ? ? flexcan 2.0b communication module ? ? ? ? u a r t s 3333 i 2 c ???? qspi ? ? ? ? pwm module ? ? ? ? real time clock ? ? ? ? 3 2 - b i t d m a t i m e r s 4444 watchdog timer (wdt) ? ? ? ? p e r i o d i c i n t e r r u p t t i m e r s ( p i t ) 4444 edge port module (eport) ? ? ? ? i n t e r r u p t c o n t r o l l e r s ( i n t c ) 2222 16-channel direct memory access (dma) ? ? ? ? flexbus external interface ? ? ? ? general purpose i/o module (gpio) ? ? ? ? jtag - ieee ? 1149.1 test access port ? ? ? ? package 196 mapbga 256 mapbga 256 mapbga 256 mapbga table 2. orderable part numbers freescale part number description package speed temperature MCF5327CVM240 mcf5327 risc microprocessor 196 mapbga 240 mhz ?40 to +85 c mcf5328cvm240 mcf5328 risc microprocessor 256 mapbga 240 mhz ?40 to +85 c mcf53281cvm240 mcf53281 risc microprocessor 256 mapbga 240 mhz ?40 to +85 c mcf5329cvm240 mcf5329 risc microprocessor 256 mapbga 240 mhz ?40 to +85 c table 1. mcf532 x family configurations (continued) module mcf5327 mcf5328 mcf53281 mcf5329
hardware design considerations mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 5 3 hardware design considerations 3.1 pll power filtering to further enhance noise isolation, an external filter is strongly recommended for pll analog v dd pins. the filter shown in figure 2 should be connected between the board v dd and the pllv dd pins. the resistor and capacitors should be placed as close to the dedicated pllv dd pin as possible. figure 2. system pll v dd power filter 3.2 usb power filtering to minimize noise, external filters are required for each of the usb power pins. the filter shown in figure 3 should be connected between the board ev dd or iv dd and each of the usbv dd pins. the resistor and cap acitors should be placed as close to the dedicated usbv dd pin as possible. figure 3. usb v dd power filter note in addition to the above filter circuitry, a 0.01 f capacitor is also recommended in parallel with those shown. 3.3 supply voltage sequenci ng and separation cautions the relationship between sdv dd and ev dd is non-critical during power-up and power-down sequences. sdv dd (2.5v or 3.3v) and ev dd are specified relative to iv dd . 3.3.1 power up sequence if ev dd /sdv dd are powered up with iv dd at 0 v, the sense circuits in the i/o pads cause all pad output drivers connected to the ev dd /sdv dd to be in a high impedance state. there is no limit on how long after ev dd /sdv dd powers up before iv dd must powered up. iv dd should not lead the ev dd , sdv dd , or pllv dd by more than 0.4 v during power ramp-up or there is board iv dd 10 0.1 f pll v dd pin 10 f gnd board ev dd 0 0.1 f usb v dd pin 10 f gnd
mcf532x coldfire ? microprocessor data sheet, rev. 5 pin assignments and reset states freescale semiconductor 6 high current in the internal es d protection diodes. the rise times on the power supplies should be slower than 500 us to avoid turning on the internal esd protection clamp diodes. 3.3.2 power down sequence if iv dd /pllv dd are powered down first, sense circuits in the i/o pads cause all output drivers to be in a high impedance state. there is no limit on how long after iv dd and pllv dd power down before ev dd or sdv dd must power down. iv dd should not lag ev dd , sdv dd , or pllv dd going low by more than 0.4 v during power down or there is undesired high current in the esd protection diodes. there are no requiremen ts for the fall times of the power supplies. the recommended power down sequence is as follows: 1. drop iv dd /pllv dd to 0 v. 2. drop ev dd /sdv dd supplies. 4 pin assignments and reset states 4.1 signal multiplexing the following table lists all the mcf532 x pins grouped by function. the dir column is the direction for the primary function of the pin only. refer to section 7, ?package information ,? for package diagrams. for a mo re detailed discussion of the mcf532 x signals, consult the mcf5329 reference manual (mcf5329rm). note in this table and throughout this document, a single signal within a group is designated without square brackets (i.e., a23), while designations for multiple signals within a group use brackets (i.e., a[23:21]) an d is meant to include all signa ls within the two bracketed numbers when these numbers are separated by a colon. note the primary functionality of a pin is not necessa rily its default functionality. pins that are muxed with gpio default to their gpio functionality. table 3. mcf5327/8/9 signal information and muxing signal name gpio alternate 1 alternate 2 dir. 1 voltage domain mcf5327 196 mapbga mcf5328 256 mapbga mcf53281 mcf5329 256 mapbga reset reset 2 ? ? ? i evdd j11 n15 n15 rstout ? ? ? o evdd p14 p14 p14 clock extal ? ? ? i evdd l14 p16 p16 xtal 2 ? ? ? o evdd k14 n16 n16 extal32k ? ? ? i evdd m11 p13 p13 xtal32k ? ? ? o evdd n11 r13 r13 fb_clk ? ? ? o sdvdd l1 t2 t2
pin assignments and reset states mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 7 mode selection rcon 2 ? ? ? i evdd m7 m8 m8 dramsel ? ? ? i evdd g11 h12 h12 flexbus a[23:22] ? fb_cs [5:4] ? o sdvdd b11,c11 c13, d13 c13, d13 a[21:16] ? ? ? o sdvdd b12, a12, d11, c12, b13, a13 e13, a14, b14, c14, a15, b15 e13, a14, b14, c14, a15, b15 a[15:14] ? sd_ba[1:0] 3 ?o sdvdd a14, b14 d14, b16 d14, b16 a[13:11] ? sd_a[13:11] 3 ?o sdvdd c13, c14, d12 c15, c16, d15 c15, c16, d15 a10 ? ? ? o sdvdd d13 d16 d16 a[9:0] ? sd_a[9:0] 3 ?o sdvdd d14, e11?14, f11?f14, g14 e14?e16, f13?f16, g16? g14 e14?e16, f13?f16, g16? g14 d[31:16] ? sd_d[31:16] 4 ? i/o sdvdd h3?h1, j4?j1, k1, l4, m2, m3, n1, n2, p1, p2, n3 m1?m4, n1?n4, t3, p4, r4, t4, n5, p5, r5, t5 m1?m4, n1?n4, t3, p4, r4, t4, n5, p5, r5, t5 d[15:1] ? fb_d[31:17] 4 ? i/o sdvdd f4?f1, g5?g2, l5, n4, p4, m5, n5, p5, l6 j3?j1, k4?k1, l2, r6, n7, p7, r7, t7, p8, r8 j3?j1, k4?k1, l2, r6, n7, p7, r7, t7, p8, r8 d0 2 ? fb_d[16] 4 ? i/o sdvdd m6 t8 t8 be/bwe [3:0] pbe[3:0] sd_dqm [3:0] 3 ? o sdvdd h4, p3, g1, m4 l4, p6, l3, n6 l4, p6, l3, n6 oe pbusctl3 ? ? o sdvdd p6 r9 r9 ta 2 pbusctl2 ? ? i sdvdd g13 g13 g13 r/w pbusctl1 ? ? o sdvdd n6 n8 n8 ts pbusctl0 dack0 ?o sdvdd d2 h4 h4 chip selects fb_cs [5:4] pcs[5:4] ? ? o sdvdd ? b13, a13 b13, a13 fb_cs [3:1] pcs[3:1] o sdvdd a11, d10, c10 a12, b12, c12 a12, b12, c12 fb_cs0 ???o sdvdd b10 d12 d12 table 3. mcf5327/8/9 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 voltage domain mcf5327 196 mapbga mcf5328 256 mapbga mcf53281 mcf5329 256 mapbga
mcf532x coldfire ? microprocessor data sheet, rev. 5 pin assignments and reset states freescale semiconductor 8 sdram controller sd_a10 ? ? ? o sdvdd l2 p2 p2 sd_cke ? ? ? o sdvdd e1 h2 h2 sd_clk ? ? ? o sdvdd k3 r1 r1 sd_clk ???o sdvdd k2 r2 r2 sd_cs1 ???o sdvdd ? j4 j4 sd_cs0 ???o sdvdd e2 h1 h1 sd_dqs3 ? ? ? o sdvdd h5 l1 l1 sd_dqs2 ? ? ? o sdvdd k6 t6 t6 sd_scas ???o sdvdd l3 p3 p3 sd_sras ???o sdvdd m1 r3 r3 sd_sdr_dqs ? ? ? o sdvdd k4 p1 p1 sd_we ???o sdvdd d1 h3 h3 external interrupts port 5 irq7 2 pirq7 2 ? ? i evdd j13 j13 j13 irq6 2 pirq6 2 usbhost_ vbus_en ? i evdd ? j14 j14 irq5 2 pirq5 2 usbhost_ vbus_oc ? i evdd ? j15 j15 irq4 2 pirq4 2 ssi_mclk ? i evdd l13 j16 j16 irq3 2 pirq3 2 ? ? i evdd m14 k14 k14 irq2 2 pirq2 2 usb_clkin ? i evdd m13 k15 k15 irq1 2 pirq1 2 dreq1 2 ssi_clkin i evdd n13 k16 k16 fec fec_mdc pfeci2c3 i2c_scl 2 ? o evdd ? c1 c1 fec_mdio pfeci2c2 i2c_sda 2 ? i/o evdd ? c2 c2 fec_txclk pfech7 ? ? i evdd ? a2 a2 fec_txen pfech6 ? ? o evdd ? b2 b2 fec_txd0 pfech5 ulpi_data0 ? o evdd ? e4 e4 fec_col pfech4 ulpi_clk ? i evdd ? a8 a8 fec_rxclk pfech3 ulpi_nxt ? i evdd ? c8 c8 fec_rxdv pfech2 ulpi_stp ? i evdd ? d8 d8 fec_rxd0 pfech1 ulpi_data4 ? i evdd ? c6 c6 table 3. mcf5327/8/9 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 voltage domain mcf5327 196 mapbga mcf5328 256 mapbga mcf53281 mcf5329 256 mapbga
pin assignments and reset states mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 9 fec_crs pfech0 ulpi_dir ? i evdd ? b8 b8 fec_txd[3:1] pfecl[7:5] ulpi_data[3:1] ? o evdd ? d3?d1 d3?d1 fec_txer pfecl4 ? ? o evdd ? b1 b1 fec_rxd[3:1] pfecl[3:1] ulpi_data[7:5] ? i evdd ? e7, a6, b6 e7, a6, b6 fec_rxer pfecl0 ? ? i evdd ? d4 d4 lcd controller lcd_d17 plcddh1 cantx ? o evdd ? ? c9 lcd_d16 plcddh0 canrx ? o evdd ? ? d9 lcd_d17 plcddh1 ? ? o evdd a6 c9 ? lcd_d16 plcddh0 ? ? o evdd b6 d9 ? lcd_d15 plcddm7 ? ? o evdd c6 a7 a7 lcd_d14 plcddm6 ? ? o evdd d6 b7 b7 lcd_d13 plcddm5 ? ? o evdd a5 c7 c7 lcd_d12 plcddm4 ? ? o evdd b5 d7 d7 lcd_d[11:8] plcddm[3:0] ? ? o evdd c5, d5, a4, b4 d6, e6, a5, b5 d6, e6, a5, b5 lcd_d7 plcddl7 ? ? o evdd c4 c5 c5 lcd_d6 plcddl6 ? ? o evdd b3 d5 d5 lcd_d5 plcddl5 ? ? o evdd a3 a4 a4 lcd_d4 plcddl4 ? ? o evdd a2 a3 a3 lcd_d[3:0] plcddl[3:0] ? ? o evdd d4, c3, d3, b2 b4, c4, b3, c3 b4, c4, b3, c3 lcd_acd/ lcd_oe plcdctlh0 ? ? o evdd d7 b9 b9 lcd_cls plcdctll7 ? ? o evdd c7 a9 a9 lcd_contrast plcdctll6 ? ? o evdd b7 d10 d10 lcd_flm/ lcd_vsync plcdctll5 ? ? o evdd a7 c10 c10 lcd_lp/ lcd_hsync plcdctll4 ? ? o evdd a8 b10 b10 lcd_lsclk plcdctll3 ? ? o evdd b8 a10 a10 lcd_ps plcdctll2 ? ? o evdd c8 a11 a11 lcd_rev plcdctll1 ? ? o evdd d8 b11 b11 lcd_spl_spr plcdctll0 ? ? o evdd b9 c11 c11 table 3. mcf5327/8/9 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 voltage domain mcf5327 196 mapbga mcf5328 256 mapbga mcf53281 mcf5329 256 mapbga
mcf532x coldfire ? microprocessor data sheet, rev. 5 pin assignments and reset states freescale semiconductor 10 usb host & usb on-the-go usbotg_m ? ? ? i/o usb vdd g12 l15 l15 usbotg_p ? ? ? i/o usb vdd h13 l16 l16 usbhost_m ? ? ? i/o usb vdd k13 m15 m15 usbhost_p ? ? ? i/o usb vdd j12 m16 m16 flexcan (mcf53281 & mcf5329 only) canrx and cantx do not have dedicated bond pads. please refer to the following pins for muxing: i2c_sda, ssi_rxd, or lcd_d16 for canrx and i2c_scl, ssi_txd, or lcd_d17 for cantx. pwm pwm7 ppwm7 ? ? i/o evdd ? h13 h13 pwm5 ppwm5 ? ? i/o evdd ? h14 h14 pwm3 ppwm3 dt3out dt3in i/o evdd h14 h15 h15 pwm1 ppwm1 dt2out dt2in i/o evdd j14 h16 h16 ssi ssi_mclk pssi4 ? ? i/o evdd ? g4 g4 ssi_bclk pssi3 u2cts pwm7 i/o evdd ? f4 f4 ssi_fs pssi2 u2rts pwm5 i/o evdd ? g3 g3 ssi_rxd 2 pssi1 u2rxd canrx i evdd ? ? g2 ssi_txd 2 pssi0 u2txd cantx o evdd ? ? g1 ssi_rxd 2 pssi1 u2rxd ? i evdd ? g2 ? ssi_txd 2 pssi0 u2txd ? o evdd ? g1 ? i 2 c i2c_scl 2 pfeci2c1 cantx u2txd i/o evdd ? ? f3 i2c_sda 2 pfeci2c0 canrx u2rxd i/o evdd ? ? f2 i2c_scl 2 pfeci2c1 ? u2txd i/o evdd e3 f3 ? i2c_sda 2 pfeci2c0 ? u2rxd i/o evdd e4 f2 ? dma dack [1:0] and dreq [1:0] do not have dedicated bond pads. please refer to the following pins for muxing: ts for dack0 , dt0in for dreq0 , dt1in for dack1 , and irq1 for dreq1 . table 3. mcf5327/8/9 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 voltage domain mcf5327 196 mapbga mcf5328 256 mapbga mcf53281 mcf5329 256 mapbga
pin assignments and reset states mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 11 qspi qspi_cs2 pqspi5 u2rts ? o evdd p10 t12 t12 qspi_cs1 pqspi4 pwm7 usbotg_ pu_en o evdd l11 t13 t13 qspi_cs0 pqspi3 pwm5 ? o evdd ? p11 p11 qspi_clk pqspi2 i2c_scl 2 ? o evdd n10 r12 r12 qspi_din pqspi1 u2cts ? i evdd l10 n12 n12 qspi_dout pqspi0 i2c_sda ? o evdd m10 p12 p12 uarts u1cts puartl7 ssi_bclk ? i evdd c9 d11 d11 u1rts puartl6 ssi_fs ? o evdd d9 e10 e10 u1txd puartl5 ssi_txd 2 ? o evdd a9 e11 e11 u1rxd puartl4 ssi_rxd 2 ? i evdd a10 e12 e12 u0cts puartl3 ? ? i evdd p13 r15 r15 u0rts puartl2 ? ? o evdd n12 t15 t15 u0txd puartl1 ? ? o evdd p12 t14 t14 u0rxd puartl0 ? ? i evdd p11 r14 r14 note: the uart2 signals are multiplexed on the qspi, ssi, dma timers, and i2c pins. dma timers dt3in ptimer3 dt3out u2rxd i evdd c1 f1 f1 dt2in ptimer2 dt2out u2txd i evdd b1 e1 e1 dt1in ptimer1 dt1out dack1 i evdd a1 e2 e2 dt0in ptimer0 dt0out dreq0 2 i evdd c2 e3 e3 bdm/jtag 6 jtag_en 7 ? ? ? i evdd l12 m13 m13 dsclk ? trst 2 ? i evdd n14 p15 p15 pstclk ? tclk 2 ? o evdd l7 t9 t9 bkpt ? tms 2 ? i evdd m12 r16 r16 dsi ? tdi 2 ? i evdd k12 n14 n14 dso ? tdo ? o evdd n9 n11 n11 ddata[3:0] ? ? ? o evdd n7, p7, l8, m8 n9, p9, n10, p10 n9, p9, n10, p10 table 3. mcf5327/8/9 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 voltage domain mcf5327 196 mapbga mcf5328 256 mapbga mcf53281 mcf5329 256 mapbga
mcf532x coldfire ? microprocessor data sheet, rev. 5 pin assignments and reset states freescale semiconductor 12 pst[3:0] ? ? ? o evdd n8, p8, l9, m9 r10, t10, r11, t11 r10, t10, r11, t11 test test 7 ? ? ? i evdd e10 a16 a16 pll_test 8 ? ? ? i evdd ? n13 n13 power supplies evdd ? ? ? ? ? e6, e7, f5?f7, h9, j8, j9, k8, k9, k11 e8, f5?f8, g5, g6, h5, h6, j11, k11, k12, l9?l11, m9, m10 e8, f5?f8, g5, g6, h5, h6, j11, k11, k12, l9?l11, m9, m10 ivdd ? ? ? ? ? e5, k5, k10, j10 e5, g12, m5, m11, m12 e5, g12, m5, m11, m12 pll_vdd ? ? ? ? ? h10 j12 j12 sd_vdd ? ? ? ? ? e8, e9, f8?f10, j5?j7, k7 e9, f9?f11, g11, h11, j5, j6, k5, k6, l5?l8, m6, m7 e9, f9?f11, g11, h11, j5, j6, k5, k6, l5?l8, m6, m7 usb_vdd ? ? ? ? ? g10 l14 l14 vss ? ? ? ? ? g6?g9, h6?h8, p9 g7?g10, h7?h10, j7?10, k7?k10, l12, l13 g7?g10, h7?h10, j7?10, k7?k10, l12, l13 pll_vss ? ? ? ? ? h11 k13 k13 usb_vss ? ? ? ? ? h12 m14 m14 1 refers to pin?s primary function. 2 pull-up enabled internally on this signal for this mode. 3 the sdram functions of these signals are not programmable by the user. they are dynamically switched by the processor when accessing sdram memory space and are included here for completeness. 4 primary functionality selected by asserting the dramsel signal (sdr mode). alternate functionality selected by negating the dramsel signal (ddr mode). the gpio module is not responsible for assigning these pins. 5 gpio functionality is determined by the edge port module. the gpio module is only responsible for assigning the alternate functions. 6 if jtag_en is asserted, these pins default to alternate 1 (jtag) functionality. the gpio module is not responsible for assigning these pins. 7 pull-down enabled internally on this signal for this mode. 8 must be left floating for proper operation of the pll. table 3. mcf5327/8/9 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 voltage domain mcf5327 196 mapbga mcf5328 256 mapbga mcf53281 mcf5329 256 mapbga
pin assignments and reset states mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 13
mcf532x coldfire ? microprocessor data sheet, rev. 5 pin assignments and reset states freescale semiconductor 14 note 4.2 pinout?256 mapbga figure 4 shows a pinout of the mcf5328cvm240, mcf53281cvm240, and mcf5329cvm240 devices. note the pin at location n13 (pll_test) must be left floating or improper operation of the pll module occurs. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a nc fec_ txclk lcd_ d4 lcd_ d5 lcd_ d9 fec_ rxd2 lcd_ d15 fec_ col lcd_ cls lcd_ lsclk lcd_ ps fb_cs3 fb_cs4 a20 a17 test a b fec_ txer fec_ txen lcd_ d1 lcd_ d3 lcd_ d8 fec_ rxd1 lcd_ d14 fec_ crs lcd_ acd/oe lcd_lp/ hsync lcd_ rev fb_cs2 fb_cs5 a19 a16 a14 b c fec_ mdc fec_ mdio lcd_ d0 lcd_ d2 lcd_ d7 fec_ rxd0 lcd_ d13 fec_ rxclk lcd_ d17 lcd_flm/ vsync lcd_ spl_spr fb_cs1 a23 a18 a13 a12 c d fec_ txd1 fec_ txd2 fec_ txd3 fec_ rxer lcd_ d6 lcd_ d11 lcd_ d12 fec_ rxdv lcd_ d16 lcd_con trast u1cts fb_cs0 a22 a15 a11 a10 d edt2in dt1in dt0in fec_ txd0 ivdd lcd_ d10 fec_ rxd3 evdd sd_vdd u1rts u1txd u1rxd a21 a9 a8 a7 e fdt3in i2c_ sda i2c_ scl ssi_ bclk evdd evdd evdd evdd sd_vdd sd_vdd sd_vdd nc a6 a5 a4 a3 f g ssi_ txd ssi_ rxd ssi_fs ssi_ mclk evdd evdd vss vss vss vss sd_vdd ivdd ta a0 a1 a2 g h sd_ cs0 sd_cke sd_we ts evdd evdd vss vss vss vss sd_vdd dram sel pwm7 pwm5 pwm3 pwm1 h j d13 d14 d15 sd_cs1 sd_vdd sd_vdd vss vss vss vss evdd pll_ vdd irq7 irq6 irq5 irq4 j k d9 d10 d11 d12 sd_vdd sd_vdd vss vss vss vss evdd evdd pll_ vss irq3 irq2 irq1 k l sd_ dqs3 d8 be/ bwe1 be/ bwe3 sd_vdd sd_vdd sd_vdd sd_vdd evdd evdd evdd vss usb_ vss usbotg _vdd usb otg_m usb otg_p l m d31 d30 d29 d28 ivdd sd_vdd sd_vdd rcon evdd evdd ivdd ivdd jtag_ en usbhost _vss usb host_m usb host_p m n d27 d26 d25 d24 d19 be/ bwe0 d6 r/w ddata3 ddata1 tdo/ dso qspi_ din pll_ test tdi/dsi reset xtal n p sd_dr _dqs sd_a10 sd_cas d22 d18 be/ bwe2 d5 d2 ddata2 ddata0 qspi_ cs0 qspi_ dout extal 32k rstout trst / dsclk extal p r sd_clk sd_clk sd_ras d21 d17 d7 d4 d1 oe pst3 pst1 qspi_ clk xtal 32k u0rxd u0cts tms/ bkpt r t nc fb_clk d23 d20 d16 sd_ dqs2 d3 d0 tclk/ pstclk pst2 pst0 qspi_ cs2 qspi_ cs1 u0txd u0rts nc t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 figure 4. mcf5328cvm240, mcf53281cvm240, and mcf5329cvm240 pinout top view (256 mapbga)
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 15 4.3 pinout?196 mapbga the pinout for the MCF5327CVM240 package is shown below. 5 electrical characteristics this document contains electrical specificat ion tables and reference timing diagrams for the mcf5329 microcontroller unit. this section contains detailed information on power cons iderations, dc/ac electrical ch aracteristics, and ac timing specifications of mcf5329. the electrical specifications are preliminary and are from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. however, for producti on silicon, these specificati ons will be met. finalized specifications will be published after co mplete characterization and devi ce qualifications have been completed. 12 3 456 7 8 9 101112 1314 a dt1in lcd_ d4 lcd_ d5 lcd_ d9 lcd_ d13 lcd_ d17 lcd_flm/ vsync lcd_lp/ hsync u1txd u1rxd fb_cs3 a20 a16 a15 a b d2tin lcd_ d0 lcd_ d6 lcd_ d8 lcd_ d12 lcd_ d16 lcd_con trast lcd_ lsclk lcd_ spl_spr fb_cs0 a23 a21 a17 a14 b c dt3in dt0in lcd_ d2 lcd_ d7 lcd_ d11 lcd_ d15 lcd_ cls lcd_ ps u1cts fb_cs1 a22 a18 a13 a12 c d sd_we ts lcd_ d1 lcd_ d3 lcd_ d10 lcd_ d14 lcd_ acd/oe lcd_ rev u1rts fb_cs2 a19 a11 a10 a9 d e sd_cke sd_cs0 i2c_scl i2c_sda ivdd evdd evdd sd_vdd sd_vdd test a8 a7 a6 a5 e f d12 d13 d14 d15 evdd evdd evdd sd_vdd sd_vdd sd_vdd a4 a3 a2 a1 f g be/ bwe1 d8 d9 d10 d11 vss vss vss vss usb otg_vdd dram sel usb otg_m ta a0 g h d29 d30 d31 be/ bwe3 sd_ dqs3 vss vss vss evdd pll_ vdd pll_ vss usbhost _vss usb otg_p pwm3 h j d25 d26 d27 d28 sd_vdd sd_vdd sd_vdd evdd evdd ivdd reset usb host_p irq7 pwm1 j k d24 sd_clk sd_clk sd_dr_ dqs ivdd sd_ dqs2 sd_vdd evdd evdd ivdd evdd tdi/dsi usb host_m xtal k l fb_clk sd_a10 sd_cas d23 d7 d1 tclk/ pstclk ddata1 pst1 qspi_ din qspi_ cs1 jtag_ en irq4 extal l m sd_ras d22 d21 be/ bwe0 d4 d0 rcon ddata0 pst0 qspi_ dout extal 32k tms/ bkpt irq2 irq3 m n d20 d19 d16 d6 d3 r/w ddata3 pst3 tdo/ dso qspi_ clk xtal 32k u0rts irq1 trst / dsclk n p d18 d17 be/ bwe2 d5 d2 oe ddata2 pst2 vss qspi_ cs2 u0rxd u0txd u0cts rstout p 12 3 456 7 8 9 101112 1314 figure 5. MCF5327CVM240 pinout top view (196 mapbga)
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 16 note the parameters specified in this mcu document supersede any values found in the module specifications. 5.1 maximum ratings table 4. absolute maximum ratings 1, 2 1 functional operating conditions are given in section 5.4, ?dc electrical specifications .? absolute maximum ratings are st ress ratings only, and functional operation at the maxima is not guaranteed. continued operation at these levels may affect device reliability or cause permanent damage to the device. 2 this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal prec autions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (v ss or ev dd ). rating symbol value unit core supply voltage iv dd ? 0.5 to +2.0 v cmos pad supply voltage ev dd ? 0.3 to +4.0 v ddr/memory pad supply voltage sdv dd ? 0.3 to +4.0 v pll supply voltage pllv dd ? 0.3 to +2.0 v digital input voltage 3 3 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance va lues for positive and negative clamp voltages, and then use the larger of the two values. v in ? 0.3 to +3.6 v instantaneous maximum current single pin limit (applies to all pins) 3, 4, 5 4 all functional non-supply pins are internally clamped to v ss and ev dd . 5 power supply must maintain regulation within operating ev dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > ev dd ) is greater than i dd , the injection current may flow out of ev dd and could result in external power supply going out of regulation. ensure external ev dd load shunts current greater than maximum injection current. this is the greatest risk when the mc u is not consuming power (ex; no clock). power supply must maintain regulation within operating ev dd range during instantaneous and operating maximum current conditions. i d 25 ma operating temperatur e range (packaged) t a (t l - t h ) ? 40 to +85 c storage temperature range t stg ? 55 to +150 c
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 17 5.2 thermal characteristics the average chip-junction temperature (t j ) in c can be obtained from: eqn. 1 where: t a = ambient temperature, c q jma = package thermal resistance, junction-to-ambient, c/w p d =p int + p i/o p int =i dd iv dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < p int and can be ignored. an approx imate relationship between p d and t j (if p i/o is neglected) is: eqn. 2 solving equations 1 and 2 for k gives: eqn. 3 table 5. thermal characteristics characteristic symbol 256mbga 196mbga unit junction to ambient, natural convection four layer board (2s2p) jma 37 1,2 1 jma and jt parameters are simulated in conformance with eia/jesd standard 51-2 for natural convection. freescale recommends the use of jma and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. system desi gners should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. conformance to the device junction temperature specific ation can be verified by physical measurement in the customer?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-6 with the board horizontal. 42 1,2 c / w junction to ambient (@200 ft/min) four layer board (2s2p) jma 34 1,2 38 1,2 c / w junction to board ? jb 27 3 3 thermal resistance between the die and the printed circuit board in conformance with jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 32 3 c / w junction to case ? jc 16 4 4 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 19 4 c / w junction to top of package ? jt 4 1,5 5 thermal characterization parameter indicating the te mperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written in conformance with psi-jt. 5 1,5 c / w maximum operating junction temperature ? t j 105 105 o c t j t a p d jma () += p d k t j 273 + () -------------------------------- - = kp d t a 273 () 2 + =
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 18 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 5.3 esd protection 5.4 dc electrical specifications table 6. esd protection characteristics 1, 2 1 all esd testing is in conformity with cdf-aec -q100 stress test qualification for automotive grade integrated circuits. 2 a device is defined as a failure if after ex posure to esd pulses the device no longer meets the device specification require ments. complete dc parametric and functional testing is performed per applicable device specificat ion at room temperature followed by hot temperature, unless specified otherwise in the device specification. characteristics symbol value units esd target for human body model hbm 2000 v table 7. dc electrical specifications characteristic symbol min max unit core supply voltage iv dd 1.4 1.6 v pll supply voltage pllv dd 1.4 1.6 v cmos pad supply voltage ev dd 3.0 3.6 v sdram and flexbus supply voltage mobile ddr/bus pad supply voltage (nominal 1.8v) ddr/bus pad supply voltage (nominal 2.5v) sdr/bus pad supply voltage (nominal 3.3v) sdv dd 1.70 2.25 3.0 1.95 2.75 3.6 v usb supply voltage usbv dd 3.0 3.6 v cmos input high voltage ev ih 2ev dd +0.3 v cmos input low voltage ev il v ss ? 0.3 0.8 v cmos output high voltage i oh = ?5.0 ma ev oh ev dd ? 0.4 ? v cmos output low voltage i ol = 5.0 ma ev ol ?0 . 4v sdram and flexbus input high voltage mobile ddr/bus input high voltage (nominal 1.8v) ddr/bus pad supply voltage (nominal 2.5v) sdr/bus pad supply voltage (nominal 3.3v) sdv ih 1.35 1.7 2 sdv dd + 0.3 sdv dd + 0.3 sdv dd + 0.3 v sdram and flexbus input low voltage mobile ddr/bus input high voltage (nominal 1.8v) ddr/bus pad supply voltage (nominal 2.5v) sdr/bus pad supply voltage (nominal 3.3v) sdv il v ss ? 0.3 v ss ? 0.3 v ss ? 0.3 0.45 0.8 0.8 v
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 19 5.5 oscillator and pll electrical characteristics sdram and flexbus output high voltage mobile ddr/bus input high voltage (nominal 1.8v) ddr/bus pad supply voltage (nominal 2.5v) sdr/bus pad supply voltage (nominal 3.3v) i oh = ?5.0 ma for all modes sdv oh sdv dd ?0.35 2.1 2.4 ? ? ? v sdram and flexbus output low voltage mobile ddr/bus input high voltage (nominal 1.8v) ddr/bus pad supply voltage (nominal 2.5v) sdr/bus pad supply voltage (nominal 3.3v) i ol = 5.0 ma for all modes sdv ol ? ? ? 0.3 0.3 0.5 v input leakage current v in = v dd or v ss , input-only pins i in ? 1.0 1.0 a weak internal pull-up device current, tested at v il max. 1 i apu ? 10 ? 130 a input capacitance 2 all input-only pins all input/output (three-state) pins c in ? ? 7 7 pf 1 refer to the signals section for pins having weak internal pull-up devices. 2 this parameter is characterized before qualification rather than 100% tested. table 8. pll electrical characteristics num characteristic symbol min. value max. value unit 1 pll reference frequency range crystal reference external reference f ref_crystal f ref_ext 12 12 25 1 40 1 mhz mhz 2 core frequency clkout frequency 2 f sys f sys/3 488 x 10 ? 6 163 x 10 ? 6 240 80 mhz mhz 3 crystal start-up time 3, 4 t cst ?1 0m s 4 extal input high voltage crystal mode 5 all other modes (external, limp) v ihext v ihext v xtal + 0.4 e vdd /2 + 0.4 ? ? v v 5 extal input low voltage crystal mode 5 all other modes (external, limp) v ilext v ilext ? ? v xtal ? 0.4 e vdd /2 ? 0.4 v v 7 pll lock time 3, 6 t lpll ? 50000 clkin 8 duty cycle of reference 3 t dc 40 60 % 9 xtal current i xtal 13m a 10 total on-chip stray capacitance on xtal c s_xtal 1.5 pf 11 total on-chip stray capacitance on extal c s_extal 1.5 pf table 7. dc electrical specifications (continued) characteristic symbol min max unit
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 20 5.6 external interface timing characteristics table 9 lists processor bus input timings. note all processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. the reference clock is the fb_clk output. all other timing relationships can be derived from these values. timings listed in table 9 are shown in figure 7 and figure 8 . 12 crystal capacitive load c l see crystal spec 13 discrete load capacitance for xtal c l_xtal 2*c l ? c s_xtal ? c pcb_xtal 7 pf 14 discrete load capacitance for extal c l_extal 2*c l ?- c s_extal ? c pcb_extal 7 pf 17 clkout period jitter, 3, 4, 7, 8, 9 measured at f sys max peak-to-peak jitter (clock edge to clock edge) long term jitter c jitter ? ? 10 tbd % f sys/3 % f sys/3 18 frequency modulation range limit 3 , 10, 11 (f sys max must not be exceeded) c mod 0.8 2.2 %f sys/3 19 vco frequency. f vco = (f ref * pfd)/4 f vco 350 540 mhz 1 the maximum allowable input clock frequency when booting with the pll enabled is 24mhz. for higher input clock frequencies the processor must boot in limp mode to avoid violating the maximum allowable cpu frequency. 2 all internal registers retain data at 0 hz. 3 this parameter is guaranteed by characterization before qualification rat her than 100% tested. 4 proper pc board layout procedures must be followed to achieve specifications. 5 this parameter is guaranteed by design rather than 100% tested. 6 this specification is the pll lock time only and does not include oscillator start-up time. 7 c pcb_extal and c pcb_xtal are the measured pcb stray capacitances on extal and xtal, respectively. 8 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via pll v dd , ev dd , and v ss and variation in crystal oscillator frequency increase the cjitter percentage for a given interval. 9 values are with frequency modulation disabled. if frequency modulation is enabled, jitter is the sum of cjitter+cmod. 10 modulation percentage applies over an interval of 10 s, or equivalently the modulation rate is 100 khz. 11 modulation range determined by hardware design. table 8. pll electrical characteristics (continued) num characteristic symbol min. value max. value unit
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 21 figure 6. general input timing requirements 5.6.1 flexbus a multi-function extern al bus interface called flexbus is pr ovided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 80mhz. it can be directly conn ected to asynchronous or synchronous devices such as external boot roms, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. for asynchronous devices a simple chip-select based interface can be used. the flexbus inte rface has six general purpose chip-selects (fb_cs [5:0]) which can be configured to be distribute d between the flexbus or sdram memory interfaces. chip-select, fb_cs0 can be dedicated to boot rom access and can be prog rammed to be byte (8 bits ), word (16 bits), or longword (32 bits) wide. control signal timing is compatible with common rom/flash memories. 5.6.1.1 flexbus ac timing characteristics the following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock. table 9. flexbus ac timing specifications num characteristic symbol min max unit ? frequency of operation f sys/3 ?80mhz fb1 clock period (fb_clk) t fbck ( t cyc) 12.5 ? ns fb2 address, data, and control ou tput valid (a[23:0], d[31:0], fb_cs [5:0], r/w , ts , be/bwe [3:0] and oe ) 1 t fbchdcv ?7.0ns fb3 address, data, and control output hold (a[23:0], d[31:0], fb_cs [5:0], r/w , ts , be/bwe [3:0], and oe ) 1 , 2 t fbchdci 1?ns invalid invalid fb_clk (80mhz) tsetup thold input setup and hold 1.5v t rise v h = v ih v l = v il 1.5v 1.5v valid t fall v h = v ih v l = v il input rise time input fall time * the timings are also valid for inputs sampled on the negative clock edge. inputs fb_clk b4 b5
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 22 note the processor drives the da ta lines during the first cl ock cycle of the transfer with the full 32-bit address. this may be ignored by standard connected devices using non-multiplexed address and data buses. however, some applications may find th is feature beneficial. the address and data busses are m uxed between the flexbus and sdram controller. at the end of the read and write bus cycles the address signals are indeterminate. figure 7. flexbus read timing fb4 data input setup t dvfbch 3.5 ? ns fb5 data input hold t difbch 0?ns fb6 transfer acknowledge (ta ) input setup t cvfbch 4?ns fb7 transfer acknowledge (ta ) input hold t cifbch 0?ns 1 timing for chip selects only applies to the fb_cs [5:0] signals. please see section 5.7.2, ?ddr sdram ac timing characteristics ? for sd_cs[3:0] timing. 2 the flexbus supports programming an extension of the address hold. please consult the reference manual for more information. table 9. flexbus ac timing specifications (continued) num characteristic symbol min max unit fb_clk fb_r/w s0 s1 s2 s3 fb_ts fb_a[23:0] fb_d[31: x] fb_cs n , fb_oe , fb_be/bwe n fb_ta data addr[31: x ] addr[23:0] fb3 fb1 fb2 fb5 fb4 fb7 fb6
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 23 figure 8. flexbus write timing 5.7 sdram bus the sdram controller supports accesses to main sdram memory from any internal master. it supports standard sdram or double data rate (ddr) sdram, but it does not support both at the same time. 5.7.1 sdr sdram ac timing characteristics the following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock, when operating in sdr mode on write cy cles and relative to sd_dqs on read cy cles. the device?s sdram controller is a ddr controller that has an sdr mode. becau se it is designed to support ddr, a dqs pulse must remain supplied to the device for each data beat of an sdr read. the processor accomplishe s this by asserting a signal named sd_sdr_dqs during read cycles. care must be taken during board design to adhere to the following guidelines and specs with regard to the sd_sdr_dqs signal and its usage. table 10. sdr timing specifications symbol characteristic symbol min max unit ? frequency of operation 1 ? 60 80 mhz sd1 clock period 2 t sdck 12.5 16.67 ns sd3 pulse width high 3 t sdckh 0.45 0.55 sd_clk sd4 pulse width low 4 t sdckh 0.45 0.55 sd_clk sd5 address, sd_cke, sd_cas , sd_ras , sd_we , sd_ba, sd_cs[1:0] - output valid t sdchacv ? 0.5 sd_clk +1.0 ns sd6 address, sd_cke, sd_cas , sd_ras , sd_we , sd_ba, sd_cs[1:0] - output hold t sdchaci 2.0 ? ns sd7 sd_sdr_dqs output valid 5 t dqsov ? self timed ns sd8 sd_dqs[3:0] input setu p relative to sd_clk 6 t dqvsdch 0.25 sd_clk 0.40 sd_clk ns fb_clk fb_r/w fb_ts fb_oe s0 s2 s3 data s1 addr[31: x ] fb_a[23:0] fb_d[31: x] addr[23:0] fb_cs n , fb_be/bwe n fb_ta fb3 fb1 fb2 fb7 fb6
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 24 figure 9. sdr write timing sd9 sd_dqs[3:2] input hold relative to sd_clk 7 t dqisdch does not apply. 0.5 sd_clk fixed width. sd10 data (d[31:0]) input setup relative to sd_clk (reference only) 8 t dvsdch 0.25 sd_clk ?n s sd11 data input hold relative to sd_clk (reference only) t disdch 1.0 ? ns sd12 data (d[31:0]) and data mask( sd_dqm[3:0]) output valid t sdchdmv ? 0.75 sd_clk + 0.5 ns sd13 data (d[31:0]) and data mask (sd_dqm[3:0]) output hold t sdchdmi 1.5 ? ns 1 the flexbus and sdram clock operates at the same frequen cy of the internal bus clock. see the pll chapter of the mcf5329 reference manual for more information on setting the sdram clock rate. 2 sd_clk is one sdram clock in (ns). 3 pulse width high plus pulse width low cannot exceed min and max clock period. 4 pulse width high plus pulse width low cannot exceed min and max clock period. 5 sd_dqs is designed to pulse 0.25 clock before the rising edge of the memory clock. this is a guideline only. subtle variation from this guideline is expected. sd_dqs only pulses dur ing a read cycle and one pulse occurs for each data beat. 6 sdr_dqs is designed to pulse 0.25 clock before the rising edge of the memory clock. this spec is a guideline only. subtle variation from this guideline is expected. sdr_dqs only pulses during a read cycle and one pulse occurs for each data beat. 7 the sdr_dqs pulse is designed to be 0.5 clock in width. the timing of the rising edge is most important. the falling edge does not affect the memory controller. 8 because a read cycle in sdr mode uses the dqs circuit within the device, it is most critical that the data valid window be centered 1/4 clk after the rising edge of dqs. ensuring that this happens results in successful sdr reads. the input setup spec is provided as guidance. table 10. sdr timing specifications (continued) symbol characteristic symbol min max unit sd_clk sddm d[31:0] a[23:0] sd_ba[1:0] cmd row sd1 sd4 col sd5 wd1 wd2 wd3 wd4 sd12 sd11 sd_cs n sd_ras sd_we sd_cas sd2 sd3
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 25 figure 10. sdr read timing 5.7.2 ddr sdram ac timing characteristics when using the sdram controller in ddr mode, the following timing numbers must be followed to properly latch or drive data onto the memory bus. all timing numbers are relative to the four dqs byte lanes. table 11. ddr timi ng specifications num characteristic symbol min max unit ? frequency of operation t ddck 60 80 mhz dd1 clock period 1 t ddsk 12.5 16.67 ns dd2 pulse width high 2 t ddckh 0.45 0.55 sd_clk dd3 pulse width low 3 t ddckl 0.45 0.55 sd_clk dd4 address, sd_cke, sd_cas , sd_ras , sd_we , sd_cs [1:0] - output valid 3 t sdchacv ? 0.5 sd_clk +1.0 ns dd5 address, sd_cke, sd_cas , sd_ras , sd_we , sd_cs [1:0] - output hold t sdchaci 2.0 ? ns dd6 write command to first dqs latching transition t cmdvdq ? 1.25 sd_clk dd7 data and data mask output setup (dq-->dqs) relative to dqs (ddr write mode) 4, 5 t dqdmv 1.5 ? ns sd_clk sd_cs n, sddm d[31:0] a[23:0], sd_ras , sd_ba[1:0] cmd row sd1 sd4 col wd1 wd2 wd3 wd4 sd9 3/4 mclk sd_sdr_dqs sd_dqs[3:2] delayed sd10 sd7 board delay sd8 board delay sd6 tdqs reference sd_clk from memories (measured at output pin) (measured at input pin) sd5 note: data driven from memories relative to delayed memory clock. sd_we sd_cas , sd2 sd3
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 26 dd8 data and data mask output hold (dqs-->dq) relative to dqs (ddr write mode) 6 t dqdmi 1.0 ? ns dd9 input data skew relative to dqs (input setup) 7 t dvdq ?1n s dd10 input data hold relative to dqs 8 t didq 0.25 sd_clk +0.5ns ?n s dd11 dqs falling edge from sdclk rising (output hold time) t dqlsdch 0.5 ? ns dd12 dqs input read preamble width t dqrpre 0.9 1.1 sd_clk dd13 dqs input read postamble width t dqrpst 0.4 0.6 sd_clk dd14 dqs output write preamble width t dqwpre 0.25 sd_clk dd15 dqs output write postamble width t dqwpst 0.4 0.6 sd_clk 1 sd_clk is one sdram clock in (ns). 2 pulse width high plus pulse width low cannot exceed min and max clock period. 3 command output valid should be 1/2 the memory bus clock (sd_ clk) plus some minor adjustments for process, temperature, and voltage variations. 4 this specification relates to the required input setup time of today?s ddr memories. the processor?s output setup should be larger than the input setup of the ddr memories. if it is not larger, the input setup on the memory is in violation. mem_data[31:24] is relative to mem_dqs[3], mem_data[23:16] is relative to mem_dqs[2], mem_ data[15:8] is relative to mem_dqs[1], and mem_[7:0] is relative mem_dqs[0]. 5 the first data beat is valid before the first rising edge of dqs and after the dqs write preamble. the remaining data beats are valid for each subsequent dqs edge. 6 this specification relates to the required hold time of today?s ddr memories. mem_data[31:24] is relative to mem_dqs[3], mem_data[23:16] is relative to mem_dq s[2], mem_data[15:8] is relative to mem_dqs[1], and mem_[7:0] is relative mem_dqs[0]. 7 data input skew is derived from each dqs clock edge. it begins with a dqs transition and ends when the last data line becomes valid. this input skew must incl ude ddr memory output skew and system leve l board skew (due to routing or other factors). 8 data input hold is derived from each dqs clock edge. it beg ins with a dqs transition and ends when the first data line becomes invalid. table 11. ddr timing specifications (continued) num characteristic symbol min max unit
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 27 figure 11. ddr write timing sd_clk sd_cs n ,sd_we , dm3/dm2 d[31:24]/d[23:16] a[13:0] sd_ras , sd_ cas cmd row dd1 dd5 dd4 col wd1 wd2 wd3 wd4 dd7 sd_dqs3/sd_dqs2 dd8 dd8 dd7 sd_clk dd3 dd2 dd6
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 28 figure 12. ddr read timing 5.8 general purpose i/o timing table 12. gpio timing 1 1 gpio pins include: irq n , pwm, uart, flexcan, and timer pins. num characteristic symbol min max unit g1 fb_clk high to gpio output valid t chpov ?10ns g2 fb_clk high to gpio output invalid t chpoi 1.5 ? ns g3 gpio input valid to fb_clk high t pvch 9?n s g4 fb_clk high to gpio input invalid t chpi 1.5 ? ns sd_clk sd_cs n ,sd_we , sd_dqs3/sd_dqs2 d[31:24]/d[23:16] a[13:0] sd_ras , sd_cas cmd row dd1 dd5 dd4 wd1 wd2 wd3 wd4 sd_dqs3/sd_dqs2 dd9 sd_clk dd3 dd2 d[31:24]/d[23:16] wd1 wd2 wd3 wd4 dd10 cl=2 cl=2.5 col dqs read preamble dqs read postamble dqs read preamble dqs read postamble cl = 2.5 cl = 2
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 29 figure 13. gpio timing 5.9 reset and configuration override timing figure 14. reset and configuration override timing note refer to the ccm chapter of the mcf5329 reference manual for more information. table 13. reset and configuration override timing num characteristic symbol min max unit r1 reset input valid to fb_clk high t rvch 9?n s r2 fb_clk high to reset input invalid t chri 1.5 ? ns r3 reset input valid time 1 1 during low power stop, the synchronizers for the reset input are bypassed and reset is asserted asynchronously to the system. thus, reset must be held a minimum of 100 ns. t rivt 5?t cyc r4 fb_clk high to rstout valid t chrov ?1 0n s r5 rstout valid to config. overrides valid t rovcv 0?n s r6 configuration override setup time to rstout invalid t cos 20 ? t cyc r7 configuration override hold time after rstout invalid t coh 0?n s r8 rstout invalid to configuration override high impedance t roicz ?1t cyc g1 fb_clk gpio outputs g2 g3 g4 gpio inputs r1 r2 fb_clk reset rstout r3 r4 r8 r7 r6 r5 configuration overrides*: r4 (rcon, override pins])
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 30 5.10 lcd controller timing specifications this sections lists the timing speci fications for the lcd controller. figure 15. lcd_lsclk to lc d_ld[17:0] timing diagram figure 16. 4/8/12/16/18 bit/pixe l tft color mode panel timing table 14. lcd_lsclk timing num parameter minimum maximum unit t1 lcd_lsclk period 25 2000 ns t2 pixel data setup time 11 ? ns t3 pixel data up time 11 ? ns note: the pixel clock is equal to lcd_lsclk / (pcd + 1). wh en it is in cstn, tft or monochrome mode with bus width is set and lcd_lsclk is equal to the pixel clock. when it is in monochrome with other bus width settings, lcd_lsclk is equal to the pixel clock divided by bus width. the polarity of lcd_lsclk and lcd_ld signals can also be programmed. t1 t2 t3 lcd_lsclk lcd_ld[17:0] line 1 line y t1 t4 t3 (1,1) (1,2) (1,x) t5 t7 t6 xmax lcd_vsync lcd_hsync lcd_oe lcd_ld[17:0] lcd_lsclk lcd_hsync lcd_oe lcd_ld[15:0] t2 display region non-display region line y
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 31 figure 17. sharp tft panel timing table 15. 4/8/12/16/18 bit/pixel tft color mode panel timing number description minimum value unit t1 end of lcd_oe to begi nning of lcd_vsync t5+t6+t7- 1 (vwait1t2)+t5+t6+t7-1 ts t2 lcd_hsync period ? xmax+t5+t6+t7 ts t3 lcd_vsync pulse width t2 vwidtht2 ts t4 end of lcd_vsync to beginning of lcd_oe 1 (vwait2t2)+1 ts t5 lcd_hsync pulse width 1 hwidth+1 ts t6 end of lcd_hsync to beginning to lcd_oe 3 hwait2+3 ts t7 end of lcd_oe to beginning of lcd_hsync 1 hwait1+1 ts note: ts is the lcd_lsclk period. lcd_vsync, lcd_hsync and lcd_oe can be programmed as active high or active low. in figure 16 , all 3 signals are active low. lcd_lsclk can be programmed to be deactivated during the lcd_vsync pulse or the lcd_oe deasserted period. in figure 16 , lcd_lsclk is always active. note: xmax is defined in number of pixels in one line. d1 d2 d320 lcd_lsclk lcd_ld lcd_spl_spr lcd_hsync lcd_cls lcd_ps lcd_rev xmax t2 d320 t1 t3 t5 t4 t7 t6 t2 t4 t7
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 32 figure 18. non-tft mode panel timing table 16. sharp tft panel timing num description minimum value unit t1 lcd_spl/lcd_spr pulse width ? 1 ts t2 end of lcd_ld of line to beginning of lcd_hsync 1 hwait1+1 ts t3 end of lcd_hsync to beginning of lcd_ld of line 4 hwait2 + 4 ts t4 lcd_cls rise delay from end of lcd_ld of line 3 cls_rise_delay+1 ts t5 lcd_cls pulse width 1 cls_hi_width+1 ts t6 lcd_ps rise delay from lcd_cls negation 0 ps_rise_delay ts t7 lcd_rev toggle delay from last lcd_ld of line 1 rev_toggle_delay+1 ts note: falling of lcd_spl/lcd_spr aligns with first lcd_ld of line. note: falling of lcd_ps aligns with rising edge of lcd_cls. note: lcd_rev toggles in every lcd_hsyn period. table 17. non-tft mode panel timing num description minimum value unit t1 lcd_hsync to lcd_vsync delay 2 hwait2 + 2 tpix t2 lcd_hsync pulse width 1 hwidth + 1 tpix t3 lcd_vsync to lcd_lsclk ? 0 t3 ts ? t4 lcd_lsclk to lcd_hsync 1 hwait1 + 1 tpix note: ts is the lcd_lsclk period while tpix is the pixel clock peri od. lcd_vsync, lcd_h sync and lcd_lsclk can be programmed as active high or active low. in figure 18 , all three signals are active high. when it is in cstn mode or monochrome mode with bus width = 1, t3 = tpix = ts. when it is in monochrome mode with bus width = 2, 4 and 8, t3 = 1, 2 and 4 tpix respectively. t1 t2 t4 t3 xmax lcd_vsync lcd_lsclk lcd_hsync lcd_ld[15:0] t2 t1 ts
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 33 5.11 usb on-the-go the mcf5329 device is compliant with industry standard usb 2.0 specification. 5.12 ulpi timing specification control and data timing requirements for the ulpi pins are given in table 18 . these timings apply in synchronous mode only. all timings are measured with either a 60 mhz input clock from the usb_clki n pin. the usb_clkin needs to maintain a 50% duty cycle. control signals and 8-bit data are always clocked on the rising edge. the ulpi interface on the mcf5329 processor is co mpliant with th e industry stan dard definition. figure 19. ulpi timing diagram 5.13 ssi timing specifications this section provides the ac timings for th e ssi in master (clocks driven) and slave modes (clocks input). all timings are give n for non-inverted serial clock polarity (ssi_tcr[tsckp] = 0, ss i_rcr[rsckp] = 0) and a n on-inverted frame sync (ssi_tcr[tfsi] = 0, ssi_rcr[rfsi] = 0). if the polarity of the clock and/ or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (ssi_bclk) and/ or the frame sync (ssi_fs) shown in the figures below. table 18. ulpi interface timing parameter symbol min max units setup time (control in, 8- bit data in) tsc, tsd ? 3.0 ns hold time (control in, 8-bit data in) thc, thd ? 1.5 ? ns output delay (control out, 8-bit data out) tdc, tdd ? 6.0 ns table 19. ssi timing ? master modes 1 num description symbol min max units s1 ssi_mclk cycle time 2 t mclk 8 t sys ?ns s2 ssi_mclk pulse width high / low 45% 55% t mclk s3 ssi_bclk cycle time 3 t bclk 8 t sys ?ns s4 ssi_bclk pulse width 45% 55% t bclk s5 ssi_bclk to ssi_fs output valid ? 15 ns tsc thc tsd tdc tdd ulpi_clk ulpi_stp ulpi_data ulpi_dir/ulpi_nxt ulpi_data thd (output) (input) (input-8bit) (output-8bit)
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 34 s6 ssi_bclk to ssi_fs output invalid -2 ? ns s7 ssi_bclk to ssi_txd valid ? 15 ns s8 ssi_bclk to ssi_txd invalid / high impedence -4 ? ns s9 ssi_rxd / ssi_fs input se tup before ssi_bclk 15 ? ns s10 ssi_rxd / ssi_fs input hold after ssi_bclk 0 ? ns 1 all timings specified with a capactive load of 25pf. 2 ssi_mclk can be generated from ssi_clkin or a divided version of the internal system clock (sysclk). 3 ssi_bclk can be derived from ssi_clkin or a divi ded version of sysclk. if the sysclk is used, the minimum divider is 6. if the ssi_clkin input is used, the programmable dividers must be set to ensure that ssi_bclk does not exceed 4 x f sys . table 20. ssi timing ? slave modes 1 1 all timings specified with a capactive load of 25pf. num description symbol min max units s11 ssi_bclk cycle time t bclk 8 t sys ?ns s12 ssi_bclk pulse width high/low 45% 55% t bclk s13 ssi_fs input setup before ssi_bclk 10 ? ns s14 ssi_fs input hold after ssi_bclk 3 ? ns s15 ssi_bclk to ssi_txd/ssi_fs output valid ? 15 ns s16 ssi_bclk to ssi_txd/ ssi_fs output invalid/high impedence -2 ? ns s17 ssi_rxd setup before ssi_bclk 10 ? ns s18 ssi_rxd hold after ssi_bclk 3 ? ns table 19. ssi timing ? master modes 1 (continued) num description symbol min max units
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 35 figure 20. ssi timing ? master modes figure 21. ssi timing ? slave modes 5.14 i 2 c input/output timing specifications table 21 lists specifications for the i 2 c input timing parameters shown in figure 22 . table 21. i 2 c input timing specifications between scl and sda num characteristic min max units i1 start condition hold time 2 ? t cyc i2 clock low period 8 ? t cyc i3 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih =2.4 v) ? 1 ms i4 data hold time 0 ? ns ssi_mclk (output) ssi_bclk (output) ssi_fs (output) ssi_txd ssi_rxd s1 s2 s2 s3 s4 s4 s5 s6 s7 s8 s8 s9 s10 s7 ssi_fs (input) s9 s10 ssi_bclk (input) ssi_fs (input) ssi_txd ssi_rxd s11 s12 s12 s14 s15 s16 s16 s17 s18 s15 s13 ssi_fs (output) s15 s16
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 36 table 22 lists specifications for the i 2 c output timing parameters shown in figure 22 . figure 22 shows timing for the values in table 22 and table 21 . figure 22. i 2 c input/output timings i5 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il =0.5 v) ? 1 ms i6 clock high time 4 ? t cyc i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 ? t cyc i9 stop condition setup time 2 ? t cyc table 22. i 2 c output timing specificat ions between scl and sda num characteristic min max units i1 1 1 output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta b l e 2 2 . the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the scl low period. the actual position is affected by the prescale and division va lues programmed into the ifdr; however, the numbers given in ta b l e 2 2 are minimum values. start condition hold time 6 ? t cyc i2 1 clock low period 10 ? t cyc i3 2 2 because i2c_scl and i2c_sda are open-collector-type ou tputs, which the processor can only actively drive low, the time i2c_scl or i2c_sda take to reach a high level depends on external signal capacitance and pull-up resistor values. i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih =2.4 v) ? ? s i4 1 data hold time 7 ? t cyc i5 3 3 specified at a nominal 50-pf load. i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 3 ns i6 1 clock high time 10 ? t cyc i7 1 data setup time 2 ? t cyc i8 1 start condition setup time (for repeated start condition only) 20 ? t cyc i9 1 stop condition setup time 10 ? t cyc table 21. i 2 c input timing specifications be tween scl and sda (continued) num characteristic min max units i2 i6 i1 i4 i7 i8 i9 i5 i3 i2c_scl i2c_sda
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 37 5.15 fast ethernet ac timing specifications mii signals use ttl signal levels compatible with devices operating at 5.0 v or 3.3 v. 5.15.1 mii receive signal timing the receiver functions correctly up to a fec_rxclk maximum frequency of 25 mh z +1%. the processor clock frequency must exceed twice the fec_rxclk frequency. table 23 lists mii receive channel timings. figure 23 shows mii receive signal timings listed in table 23 . figure 23. mii receive signal timing diagram 5.15.2 mii transmit signal timing table 24 lists mii transmit channel timings. the transmitter functions correctly up to a fec_txclk maxi mum frequency of 25 mhz +1%. the processor clock frequency must exceed twice the fec_txclk frequency. figure 24 shows mii transmit sign al timings listed in table 24 . table 23. mii receive signal timing num characteristic min max unit m1 fec_rxd[3:0], fec_rxdv, fec_rxer to fec_rxclk setup 5 ? ns m2 fec_rxclk to fec_rxd[3:0], fec_rxdv, fec_rxer hold 5 ? ns m3 fec_rxclk pulse width high 35% 65% fec_rxclk period m4 fec_rxclk pulse width low 35% 65% fec_rxclk period table 24. mii transmit signal timing num characteristic min max unit m5 fec_txclk to fec_txd[3:0], fe c_txen, fec_txer invalid 5 ? ns m6 fec_txclk to fec_txd[3:0], fec_txen, fec_txer valid ? 25 ns m7 fec_txclk pulse width high 35% 65% fec_txclk period m8 fec_txclk pulse width low 35% 65% fec_txclk period m1 m2 fec_rxclk (input) fec_rxd[3:0] (inputs) fec_rxdv fec_rxer m3 m4
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 38 figure 24. mii transmit signal timing diagram 5.15.3 mii async inputs signal timing table 25 lists mii asynchronous inputs signal timing. figure 25. mii async inputs timing diagram 5.15.4 mii serial management channel timing table 26 lists mii serial management channel timings. the fec f unctions correctly with a maximum mdc frequency of 2.5 mhz. table 25. mii async inputs signal timing num characteristic min max unit m9 fec_crs, fec_col minimum pulse width 1.5 ? fec_txclk period table 26. mii serial management channel timing num characteristic min max unit m10 fec_mdc falling edge to fec_mdio output invalid (minimum propagation delay) 0? ns m11 fec_mdc falling edge to fec_mdio output valid (max prop delay) ? 25 ns m12 fec_mdio (input) to fec_mdc rising edge setup 10 ? ns m13 fec_mdio (input) to fec_mdc rising edge hold 0 ? ns m14 fec_mdc pulse width high 40% 60% fec_mdc period m15 fec_mdc pulse width low 40% 60% fec_mdc period m6 fec_txclk (input) fec_txd[3:0] (outputs) fec_txen fec_txer m5 m7 m8 fec_crs m9 fec_col
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 39 figure 26. mii serial management channel timing diagram 5.16 32-bit timer module timing specifications table 27 lists timer module ac timings. 5.17 qspi electrical specifications table 28 lists qspi timings. table 27. timer module ac timing specifications name characteristic min max unit t1 dt0in / dt1in / dt2in / dt3in cycle time 3 ? t cyc t2 dt0in / dt1in / dt2in / dt3in pulse width 1 ? t cyc table 28. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[3:0] to qspi_clk 1 510 t cyc qs2 qspi_clk high to qspi_dout valid. ? 10 ns qs3 qspi_clk high to qspi_dou t invalid. (output hold) 2 ? ns qs4 qspi_din to qspi_clk (input setup) 9 ? ns qs5 qspi_din to qspi_clk (input hold) 9 ? ns m11 fec_mdc (output) fec_mdio (output) m12 m13 fec_mdio (input) m10 m14 m15
mcf532x coldfire ? microprocessor data sheet, rev. 5 electrical characteristics freescale semiconductor 40 figure 27. qspi timing 5.18 jtag and boundary scan timing table 29. jtag and boundary scan timing num characteristics 1 1 jtag_en is expected to be a static signal. hence, specific timing is not associated with it. symbol min max unit j1 tclk frequency of operation f jcyc dc 1/4 f sys/3 j2 tclk cycle period t jcyc 4? t cyc j3 tclk clock pulse width t jcw 26 ? ns j4 tclk rise and fall times t jcrf 03 ns j5 boundary scan input data setup time to tclk rise t bsdst 4? ns j6 boundary scan input data hold time after tclk rise t bsdht 26 ? ns j7 tclk low to boundary scan output data valid t bsdv 033 ns j8 tclk low to boundary scan output high z t bsdz 033 ns j9 tms, tdi input data setup time to tclk rise t tapbst 4? ns j10 tms, tdi input data hold time after tclk rise t tapbht 10 ? ns j11 tclk low to tdo data valid t tdodv 026 ns j12 tclk low to tdo high z t tdodz 08 ns j13 trst assert time t trstat 100 ? ns j14 trst setup time (negation) to tclk high t trstst 10 ? ns qspi_cs[3:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2
electrical characteristics mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 41 figure 28. test clock input timing figure 29. boundary scan (jtag) timing figure 30. test access port timing figure 31. trst timing tclk v il v ih j4 j4 (input) j2 j3 j3 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j7 j8 j7 j6 j5 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst j13 j14
mcf532x coldfire ? microprocessor data sheet, rev. 5 current consumption freescale semiconductor 42 5.19 debug ac timing specifications table 30 lists specifications for the debug ac timing parameters shown in figure 32 . figure 32. real-time trace ac timing figure 33. bdm serial port ac timing 6 current consumption all current consumption data is lab data measured on a single device using an evaluation board. table 31 shows the typical power consumption in low-power modes. these current m easurements are taken after executing a stop instruction. table 30. debug ac timing specification num characteristic min max units d0 pstclk cycle time 2 2 t sys = 1/f sys d1 pstclk rising to pstddata valid ? 3.0 ns d2 pstclk rising to pstddata invalid 1.5 ? ns d3 dsi-to-dsclk setup 1 ? pstclk d4 1 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of pstclk. dsclk-to-dso hold 4 ? pstclk d5 dsclk cycle time 5 ? pstclk d6 bkpt assertion time 1 ? pstclk pstclk pstddata[7:0] d0 d1 d2 past current dsclk dsi dso next current d5 d3 d4
current consumption mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 43 figure 34. current consumption in low-power modes table 31. current consumption in low-power modes 1,2 1 all values are measured with a 3.30v ev dd , 3.30v sdv dd and 1.5v iv dd power supplies. tests performed at room temperature with pins configur ed for high drive strength. 2 refer to the power management chapter in the mcf532x reference manual for more information on low-power modes. mode voltage 58 mhz (typ) 3 3 all peripheral clocks except uart0, flexbus, intc0, reset controller, pll, and edge port off before entering low power mode. all code executed from flash. 64 mhz (typ) 3 72 mhz (typ) 3 80 mhz (typ) 3 80 mhz (peak) 4 4 all peripheral clocks on before entering low power mode. all code is executed from flash. units stop mode 3 (stop 11) 5 5 see the description of the low-power control register (lcpr) in the mcf532x reference manual for more information on stop modes 0?3. 3.3 v 3.9 3.92 4.0 4.0 4.0 ma 1.5 v 1.04 1.04 1.04 1.04 1.08 stop mode 2 (stop 10) 4 3.3 v 4.69 4.72 4.8 4.8 4.8 1.5 v 2.69 2.69 2.70 2.70 2.75 stop mode 1(stop 01) 4 3.3 v 4.72 4.73 4.81 4.81 4.81 1.5 v 15.28 16.44 17.85 19.91 20.42 stop mode 0 (stop 00) 4 3.3 v 21.65 21.68 24.33 26.13 26.16 1.5 v 15.47 16.63 18.06 20.12 20.67 wait/doze 3.3 v 22.49 22.52 25.21 27.03 39.8 1.5 v 26.79 28.85 30.81 34.47 97.4 run 3.3 v 33.61 33.61 42.3 50.5 62.6 1.5 v 56.3 60.7 65.4 73.4 132.3 0 50 100 150 200 250 300 350 400 450 58 64 72 80 80(peak) fsys/3 (mhz) power consumption (mw) stop 0 - flash stop 1 - flash stop 2 - flash stop 3 - flash wait/doze - flash run - flash
mcf532x coldfire ? microprocessor data sheet, rev. 5 current consumption freescale semiconductor 44 figure 35 shows the estimated maximum power consumption. figure 35. estimated maximum power consumption table 32. typical active current consumption specifications 1 1 all values are measured with a 3.30 v ev dd , 3.30 v sdv dd and 1.5 v iv dd power supplies. tests performed at room temperature with pins configured for high drive strength. f sys/3 frequency voltage typical 2 active (flash) 2 cpu polling a status register. all periph eral clocks except uart0, flexbus, intc0, reset controller, pll, and edge port disabled. peak 3 3 peak current measured while running a while(1) loop with all modules active. unit 1.333 mhz 3.3v 7.73 7.74 ma 1.5v 2.87 3.56 2.666 mhz 3.3v 8.57 8.60 1.5v 4.37 5.52 58 mhz 3.3v 40.10 49.3 1.5v 65.90 91.70 64 mhz 3.3v 44.40 54.0 1.5v 69.50 97.0 72 mhz 3.3v 53.6 63.7 1.5v 74.6 104.7 80 mhz 3.3v 63.0 73.7 1.5v 79.6 112.9 estimated power consumption vs. core frequency 0 50 100 150 200 250 300 0 40 80 120 160 200 240 core frequency (mhz) power consumption (mw )
package information mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 45 7 package information this section contains drawings showing the pinout and th e packaging and mechanical ch aracteristics of the mcf532 x devices. note the mechanical drawings are the latest revi sions at the time of publication of this document. the most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire . 7.1 package dimensions?256 mapbga figure 36 shows mcf5328cvm240, mcf53281cvm240, and mcf5329cvm240 package dimensions. figure 36. 256 mapbga package outline x y d e laser mark for pin a1 identification in this area 0.20 metalized mark for pin a1 identification in this area m m 3 a b c d e f g h j k l m n p r t 1234567 10 11 12 13 14 15 16 e 15x e 15x b 256x m 0.25 y z m 0.10 x z s detail k view m-m rotated 90 clockwise s a z z a2 a1 4 0.15 z 0.30 256x 5 k notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.25 1.60 a1 0.27 0.47 a2 1.16 ref b 0.40 0.60 d 17.00 bsc e 17.00 bsc e 1.00 bsc s 0.50 bsc top view bottom view
mcf532x coldfire ? microprocessor data sheet, rev. 5 package information freescale semiconductor 46 7.2 package dimensions?196 mapbga figure 37 shows the MCF5327CVM240 package dimensions. figure 37. 196 mapbga package dimensions (case no. 1128a-01) x 0.20 laser mark for pin 1 identification in this area e 13x d e m s a1 a2 a 0.15 z 0.30 z z rotated 90 clockwise detail k 5 view m-m e 13x s m x 0.30 y z 0.10 z 3 b 196x metalized mark for pin 1 identification in this area 14 13 12 11 5 4 3 2 b c d e f g h j k l 4 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.32 1.75 a1 0.27 0.47 a2 1.18 ref b 0.35 0.65 d 15.00 bsc e 15.00 bsc e 1.00 bsc s 0.50 bsc y k m n p a 1 6 10 9 top view bottom view
revision history mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 47 8 revision history table 33. mcf5329ds document revision history rev. no. substantive changes date of release 0 ? initial release. 11/2005 0.1 ? added not to section 7, ?package information .? ? added top view and bottom view where appropriate in mechanical drawings and pinout figures. ? figure 6 : corrected ?fb_clk (75mhz)? label to ?fb_clk (80mhz)? 3/2006 1 ? corrected mcf5327 196m apbga ball map locations in ta b l e 5 for the following signals: rcon, d1, d0, oe, r/w, sd_dqs2, pstclk, ddata[3:0], pst[3:0], evdd, ivdd, and sd_vdd. figure 5 was correct. ? updated thermal characteristic values in ta b l e 5 . ? updated dc electricals values in ta b l e 7 . ? updated section 3.3, ?supply voltage sequencing and separation cautions ? and subsections. ? updated and added oscillator/pll characteristics in ta b l e 8 . ? ta bl e 9 : swapped min/max for fb1; removed fb8 & fb9. ? updated sdram write timing diagram, figure 9 . ? ta bl e 1 1 : added values for frequency of operation and dd1. ? reworded first paragraph in section 5.12, ?ulpi timing specification .? ? updated figure 19 . ? replaced figure & table section 5.13, ?ssi timing specifications ,? with slave & master mode versions. ? removed second sentence from section 5.15.2, ?mii transmit signal timing ,? regarding no minimum frequency requirement for txclk. ? removed third and fourth paragraphs from section 5.15.2, ?mii transmit signal timing ,? as this feature is not supported on this device. ? updated figure & table section 5.19, ?debug ac timing specifications .? ? renamed & moved previous version?s section 5.5 ?power consumption? to section 6, ?current consumption .? added additional real-world data to this section as well. 7/2007 2 ? added mcf53281 device information throughout: features list, family configuration table, ordering information table, signals description table, and relevant package diagram titles ? remove footnote 1 from ta bl e 1 1 . ? changed document type from advance information to technical data. 8/2007 3 ? corrected mcf53281 in features list table. this device contains can, but does not feature the cryptography accelerators. ? in pin-multiplexing table, moved mcf53281 label from the mcf5328 column to the mcf5329 column, because this device contains can output signals. 10/2007
mcf532x coldfire ? microprocessor data sheet, rev. 5 revision history freescale semiconductor 48 4 ? corrected pinouts in signal information and pin-muxing table for 196 mapbga device: changed d[15:1] entry from ?f4?f1, g4?g2...? to ?f4?f1, g5?g2...? changed dso/tdo entry from ?p9? to ?n9? ? corrected d0 spec in ta b l e 3 0 from 1.5 x t sys to 2 x t sys for min and max balues. ? updated flexbus read and write timing diagrams in figure 7 and figure 8 . ? removed footnote 2 from the irq[7:1] alternate functions usbhost vbus_en, usbhost vbus_oc, ssi_mclk, usb_clkin, and ssi_clkin signals in signal information and pin-muxing table. ? updated pinouts for 196 mapbga device, MCF5327CVM240 in both figure 5 and ta b l e 2 . the following locations are affected: g10?12, h12?14, j11?14, k12?13, l12?13, m12?14, n13. the following signals are affected: usbotg_vdd, usbhost_vss, usbotg_m, usbotg_p, usbhost_m, usbhost_p, dramsel, pwm3, pwm1, irq [7,4,3,2,1], reset , tdi/dsi, jtag_en, tms/bkpt . 4/2008 5 changed the following specs in ta bl e 1 0 and ta bl e 1 1 : ? minimum frequency of operation from tbd to 60mhz ? maximum clock period from tbd to 16.67 ns 11/2008 table 33. mcf5329ds document revision history (continued) rev. no. substantive changes date of release
revision history mcf532x coldfire ? microprocessor data sheet, rev. 5 freescale semiconductor 49
document number: mcf5329ds rev. 5 11/2008 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008. all rights reserved.

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